In Spring 2016, I took CMU’s 18-632 Intro to Hardware Security course with Ken Mai. The final project in the class was extremely open-ended – essentially we were told to “Form teams, propose something related to hardware security, and do it.” Most teams chose to implement a crypto algorithm (software) or design a Physically Unclonable Function (PUF) on an FPGA. In the interest of mounting a real black-hat hardware attack, I decided to try decapsulating a simple IC and reverse engineering its function.
I Need Professional Help
Professor Mai set up a meeting for me with Alexander Volynkin, a researcher at CMU’s Software Engineering Institue (SEI) who achieved national recognition for hacking the Tor network to track its users and allegedly being paid big money by the US government to do it. We met in the lobby of the SEI - one of the most intimidating places I’ve ever been - to discuss my idea. Basically, he told me to pick another project because I was unlikely to make any progress without cleanroom access and getting access to the cleanrooms at CMU is expensive and time-consuming. I was hoping he could help me out with those things, but it was clear I was going to have to figure it out on my own.
I Don’t Need Professional Help
Decapsulating and reverse engineering a chip is difficult for the following reasons:
- Getting access to the transistors requires removing the super-tough packaging material without scratching the surface of the delicate silicon wafer it contains.
- Even with 1960’s processes, transistors are small. You can’t figure out what the chip does if you can’t see the transistors!
- Most chips have many layers of wires on top of the transistors. Without ultra-specialized tools (a cleanroom), you can really only see the top level of interconnect and a little bit of what’s underneath it.
- Even if you can see all the transistors and their interconnection, you still have to detangle a complicated mess of connections to figure out what the chip does and how it does it.
I figured I could solve most of these problems by choosing an extremely simple, extremely old chip to reverse engineer. And probably breaking a lot of them. I headed to the electronics lab in the Field Robotics Center at FRC. I dug through their drawers and found a handful of SN74HC86N Quad XOR chips from the 80’s (I think). I hoped that choosing such an uncomplicated, ancient chip would give me a good chance to solve my four big problems.
Given that I have access to a machine shop – and not wanting to become horribly disfigured in an accident with concentrated nitric acid – I decided to try decapsulating the XORs by mechanical means first. I soldered three XORs to a prototyping circuit board, and attacked them with an endmill. It went terribly. The little legs of the chip were too weak to hold the chip in place against the comparatively massive cutting forces from the endmill, and as a result, any attempts to cut away the package material just pushed the chip off the board and made a mess. Enter, The Chip Clip©®™.
I spent about an hour in the FRC shop building this fixture to clamp the XOR while I milled away the packaging a few thousandths of an inch at a time. On my second try, I got lucky. After painstakingly inching (milli-inching?) the Z-axis on the mill 2 thou per pass, I managed to scrape/rip away almost all of the packaging above the approximately 1mm square silicon wafer. SUCCESS! I tried duplicating my success about six more times, but every single chip ended up getting shredded by a combination of impatience and bad luck.
Also, I probably owe someone a new endmill because I don’t think milling ceramic package material is conducive to keeping your tooling sharp. The lesson to learn here is if you’re going to abuse some tools, first make sure they belong to someone else1.
Crap I Do Need Professional Help
Once I had successfully exposed the silicon, I needed a good way to get high-resolution pictures of its surface. I could kind of make out vaguely rectangular shapes using one eyepiece of the broken microscope in the FRC electronics lab, but that was never going to work well enough for me to finally figure out how an XOR works! (Ignore the five and a half years of Electrical Engineering degrees2 I had earned up to this point.)
Long story short, I asked Professor Mai if he could help me get access to a microscope, and he introduced me to one of his grad students. The grad student took my chip to the cleanroom (yes, I know that’s cheating. Oh well), and a few days later I got back some images!
This is a 10x magnification overview of the die. There’s a flake of packaging material still obscuring the top left corner, but right away we can see some interesting features. The large square pads spaced around the perimeter of the chip are the bond wire connection locations. Tiny gold wires are ultrasonically welded to these pads and used to connect the die to the big pins on the chip package.
I also got a set of five overlapping images at 20x magnification. I stitched the images together in software, and my buddy Dan helped me reflect the bottom left corner up to cover the missing top left corner.
That’s awesome. What is it?
Now that I had an image of the die, I had to figure out how it worked! I was encouraged because almost all the connections were visible in the image, but discouraged because even for a super simple chip, it looked scarily complicated. What is all that crap?
Because the chip is 4-way symmetric, I decided to start my reverse engineering in the bottom left corner – where the microscope image is clearest.
I was temporarily confused by the strange interleaved connections all over the chip, but I quickly realized that each block of these finger-like wires formed a single transistor. Using two simple facts, I was able to distinguish and label the majority of the P-type and N-type transistors.
- Charge carriers don’t move as easily through the channel of a P-type FET as they move through the channel of an N-type FET. For this (over-simplified) reason, P-type FETs need to be larger than N-type FETs.
- In CMOS designs, the P-FETs are connected to Vcc, and N-FETs are connected to ground.
I thresholded the image to black and white, printed three or four of them, and sat on the floor coloring the connections with colored pencils for a while. Eventually, that got tedious, so I used gimp’s bucket tool to flood fill connections in the image. This is what I came up with.
At first, I expected this circuit to be a normal XOR CMOS circuit, but by comparing the number of N- and P-type transistors, I could tell this wasn’t the XOR circuit I would draw if you asked me to draw a CMOS XOR. Next, I thought this might be a transmission gate XOR or something tricky like that. Eventually, I realized that I was looking at a transmission gate XNOR with a big inverter on the output. Transmission gates are cool because they can help reduce the transistor count of your logic circuit, but they aren’t able to source/sink a lot of current. The big inverter on the output buffers the signal, allowing it to push/pull a lot harder, and it also inverts the logic level of the XNOR to yield the correct XOR behavior.
Another tricky aspect of this circuit is the double inversion of the inputs. The transmission gate XNOR requires two inputs and their complements. I expected to find two inverters on the inputs, but I found four! It turns out TI was inverting once to get the signal complements, and inverting that to get the original signal back. The reason TI does this, is they want to reduce the load that this XOR imposes on the circuit that’s driving it. Because TI double inverts the inputs, a circuit trying to drive the XOR only “sees” the capacitance of a small inverter’s gate, rather than the large capacitance of the big transmission gate transistors.
As a short aside, I hate when people talk about what a circuit “sees”. What the heck does that mean? In this case, the input to the XOR looks like a little bucket of charge. If you want to change the input to the XOR, you have to either fill the bucket with electrons, or drain the electrons out of the bucket. TI designed their chip in a way that minimizes the size of the bucket, so that circuits using the XOR don’t need a huge hose for filling and draining buckets. The circuit using the XOR “sees” a small bucket.
Wow. For such a simple circuit, that was A LOT of work. Companies like ChipWorks do this with REAL chips with many many layers of interconnect and BILLIONS of transistors that are 1000x smaller than the transistors in my XOR. Having done a tiny bit of hardware reverse engineering, I have a lot more respect for everyone involved. The guys that design these chips clearly put a lot of effort into producing a good chip, and the guys reverse engineering the chips must have an infinite capacity for tedium.
Is it okay to blockquote something you said yourself in the same article you said it in? Regardless, don’t tell my dad I said that. I don’t actually make a habit of abusing tools - especially when they aren’t mine! ↩
Speaking of degrees, I once answered “degrees Celsius” to a question in a Scholar’s Bowl Competition (team Jeopardy! for High School kids). The other team appealed, claiming that “degrees Celsius” is incorrect because “degrees” implies Fahrenheit - as in “32 degrees Fahrenheit”. We lost the points for that question, and I just now realized how bogus an argument that was. But I digest. ↩